The present invention relates generally to semiconductor devices and their fabrication, and more particularly, to techniques for analyzing circuitry within an integrated circuit die attached to a package substrate.
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages.
As the manufacturing processes for semiconductor devices and integrated circuit (IC) dies increase in difficulty, methods for testing and debugging these devices become increasingly important. Not only is it important to ensure that individual chips are functional, it is also important to ensure that batches of chips perform consistently. In addition, the ability to detect a defective manufacturing process early is helpful for reducing the number of defective devices manufactured.
To increase the number of pad sites available for a die, to reduce the electrical path to the pad sites, and to address other problems, various chip packaging techniques have been developed. One of these techniques is referred to as controlled collapse chip connection or flip chip packaging. In flip chip packaged dies, transistors and other circuitry are generally formed in a very thin layer at a circuit side or front side of the die. The die is flipped so that the circuit side is positioned very near the package, and an opposing back side of the die remains exposed. Electrical connection from the die to the package is made between the flipped circuit side and the package, and an underfill region is formed between the die and the package. The underfill protects the circuit connections between the die and the package, and helps to hold the packaged die together.
The positioning of the circuit side near the package provides many advantages. However, in some instances, orienting the die with the circuit side face down on a substrate is disadvantageous. Due to this orientation of the die, the transistors and circuitry near the circuit side are not directly accessible for testing, modification or other purposes. Therefore, access to the transistors and circuitry near the circuit side is from the back side of the chip.
In many applications, accessing the circuitry includes etching a portion of the backside of the die. However, such etching can erode the underfill. When the underfill is eroded, the die is more susceptible to chipping, and the circuitry between the die and the package can be exposed. This can result in damage to the die, which can cause problems, for example, during analysis of the die.
One particular type of integrated circuit die includes silicon on insulator (SOI) structure. SOI structure includes a buried insulator, such as oxide, and circuitry formed on the insulator. In flip chip and other applications, the circuitry is often accessed through the insulator portion of the SOI structure, where substrate over the insulator has to be removed in order to expose the insulator. In some applications, the die is etched to expose the insulator using an etch chemistry, such as an etch chemistry including TMAH, that erodes the underfill.
The present invention is directed to approaches for addressing challenges discussed above, including challenges to etching IC dies, as exemplified in a number of implementations and applications, some example aspects of which are summarized below.
According to an example embodiment of the present invention, an IC die coupled to a package substrate is etched in a manner that inhibits the erosion of an underfill portion adjacent to the package and around the die periphery. A protective coating that is adapted to inhibit underfill erosion by etch chemicals is formed over some or all of the underfill. After the protective coating is formed, the die is etched while using the protective coating to inhibit erosion of the underfill. In this manner, problems related to erosion of the underfill, damage to the die and those discussed above are reduced or even eliminated.
According to a more particular example embodiment of the present invention, a flip chip packaged die having silicon on insulator (SOI) structure is etched and analyzed in a manner that inhibits erosion of an underfill portion of the packaged die structure. The flip chip die has a circuit side and a back side, the circuit side faces the package substrate and the underfill portion is between the die and the package and around a periphery of the circuit side of the die. A portion of the back side of the die is removed and a portion of the die is exposed. A protective coating adapted to inhibit erosion of the underfill in the presence of TMAH is formed covering the underfill and a portion of the exposed portion of the die. After the protective coating is formed, the die is etched using a TMAH solution while using the protective coating to inhibit erosion of the underfill, and a portion of the insulator of the SOI structure is exposed. The die is then analyzed via the exposed insulator portion.
In another example embodiment of the present invention, a system is adapted for etching an IC die coupled to a package substrate and having an underfill portion adjacent to the package and around the die periphery. The system includes a deposition arrangement adapted to form a protective coating over the underfill that inhibits erosion of the underfill during etching. An etching arrangement is adapted to etch a portion of the IC die, after forming the protective coating, while using the protective coating to inhibit erosion of the underfill.
The above summary is not intended to describe each illustrated embodiment or every implementation. The figures and detailed description that follow more particularly exemplify these embodiments.